{"id":1922,"date":"2026-06-25T16:43:00","date_gmt":"2026-06-25T16:43:00","guid":{"rendered":"https:\/\/futurenews24.com\/index.php\/2026\/06\/25\/scaling-ai-inference-across-multiple-gpus-using-nvidia-tensorrt-with-multi-device-inference-support\/"},"modified":"2026-07-05T21:59:06","modified_gmt":"2026-07-05T21:59:06","slug":"scaling-ai-inference-across-multiple-gpus-using-nvidia-tensorrt-with-multi-device-inference-support","status":"publish","type":"post","link":"https:\/\/futurenews24.com\/index.php\/2026\/06\/25\/scaling-ai-inference-across-multiple-gpus-using-nvidia-tensorrt-with-multi-device-inference-support\/","title":{"rendered":"Scaling AI Inference Throughout A number of GPUs Utilizing NVIDIA TensorRT with Multi-System Inference Help"},"content":{"rendered":"<p><br \/>\n<\/p>\n<div>\n<p class=\"wp-block-paragraph\">Generative AI workloads are quickly outgrowing the reminiscence and compute price range of single GPUs. For inference builders constructing media era pipelines, the problem is scaling throughout a number of units with out sacrificing the crucial optimizations\u2014like kernel fusions, reminiscence planning, and quantization\u2014that NVIDIA TensorRT delivers for manufacturing deployments.\u00a0<\/p>\n<p class=\"wp-block-paragraph\">Multi-device inference help, a brand new function launched in TensorRT 11.0, brings native high-performance multi-GPU inference to the TensorRT runtime, enabling multi-device manufacturing deployments focusing on edge units.<\/p>\n<p class=\"wp-block-paragraph\">Combining the multi-device inference help in TensorRT with Torch-TensorRT, builders can convert and deploy large PyTorch fashions out-of-framework, shattering single-device reminiscence and compute limits.<\/p>\n<p class=\"wp-block-paragraph\">Obtain TensorRT 11.0 with multi-device inference help from NVIDIA Developer Portal to unlock native, high-performance multi-device acceleration to your fashions.<\/p>\n<h2 id=\"nvidia_nccl_the_transport_layer_for_distributed_inference\" class=\"wp-block-heading\">NVIDIA NCCL: The transport layer for distributed inference<\/h2>\n<p class=\"wp-block-paragraph\">The NVIDIA Collective Communications Library (NCCL) gives high-performance multi-GPU and multi-node collective operations powering large-scale mannequin coaching throughout hundreds of GPUs. NCCL mechanically selects the optimum transport for a given topology, abstracting NVIDIA NVLink, NVIDIA NVSwitch, PCIe, and InfiniBand behind a uniform interface. By integrating straight with NCCL, TensorRT inherits this transport optimization for inference workloads, when operating multi-device inference. For extra info on NCCL, see https:\/\/developer.nvidia.com\/nccl.<\/p>\n<p class=\"wp-block-paragraph\">The brand new multi-device function covers the total set of NVIDIA NCCL distributed collectives: AllReduce, Broadcast, Cut back, AllGather, ReduceScatter, AlltoAll, Collect, and Scatter.<\/p>\n<h2 id=\"parallelism_strategies_for_distributed_inference\" class=\"wp-block-heading\">Parallelism methods for distributed inference<\/h2>\n<p class=\"wp-block-paragraph\">Distributed inference might be expressed utilizing a number of parallelism methods, every with totally different trade-offs between reminiscence financial savings, compute scaling, and communication overhead. The most typical methods are tensor parallelism and context parallelism.<\/p>\n<h3 id=\"tensor_parallelism\" class=\"wp-block-heading\">Tensor parallelism<\/h3>\n<p class=\"wp-block-paragraph\">In tensor parallelism, the weights of a single layer are partitioned throughout GPUs. Every GPU computes a shard of the layer\u2019s matrix multiplication after which combines partial outcomes via a collective to supply the total output. This reduces per-device reminiscence weight, making it the pure (and sometimes the one) selection when a person layer\u2019s weights exceed the reminiscence of a single GPU, unbiased of the enter sequence size or batch dimension.\u00a0<\/p>\n<p class=\"wp-block-paragraph\">In a transformer block, column-parallel projections (for instance, QKV and the MLP up-projection) are paired with row-parallel projections (the eye output and the MLP down-projection) so that every block requires solely a single AllReduce, preserving communication overhead bounded.<\/p>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391ae5c5&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391ae5c5\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1938\" height=\"416\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections.webp\" alt=\"An image showing the side-by-side comparison of column-wise and row-wise parallel projections.\" class=\"wp-image-119047\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections.webp 1938w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-179x38.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-300x64.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-768x165.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-625x134.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-1536x330.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-645x138.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-500x107.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-160x34.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-362x78.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-512x110.png 512w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-1024x220.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-960x206.png 960w\" sizes=\"(max-width: 1938px) 100vw, 1938px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1938\" height=\"416\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections.webp\" alt=\"An image showing the side-by-side comparison of column-wise and row-wise parallel projections.\" class=\"lazyload wp-image-119047\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections.webp 1938w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-179x38.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-300x64.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-768x165.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-625x134.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-1536x330.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-645x138.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-500x107.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-160x34.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-362x78.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-512x110.png 512w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-1024x220.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Projections-960x206.png 960w\" data-sizes=\"(max-width: 1938px) 100vw, 1938px\"\/><figcaption class=\"wp-element-caption\">Determine 1. Column-wise and row-wise parallel projections<\/figcaption><\/figure>\n<\/div>\n<h3 id=\"context_parallelism\u00a0\" class=\"wp-block-heading\">Context parallelism\u00a0<\/h3>\n<p class=\"wp-block-paragraph\">In context parallelism, the enter sequence is partitioned throughout GPUs alongside the sequence dimension. Every GPU processes solely a slice of the sequence, whereas collective operations make the worldwide sequence obtainable the place wanted, reminiscent of throughout consideration. Context parallelism is especially efficient for long-sequence workloads, the place consideration\u2019s quadratic scaling with sequence size makes it the dominant client of compute and reminiscence.<\/p>\n<p class=\"wp-block-paragraph\">It is usually an particularly pure match for diffusion and DiT fashions, whose bidirectional consideration sidesteps the load-imbalance points that come up with causal masks.<\/p>\n<p class=\"wp-block-paragraph\">Learn the Context Parallelism for Scalable Million-Token Inference article for added particulars on context parallelism.<\/p>\n<p class=\"wp-block-paragraph\">NVIDIA TensorRT 11.0 introduces help for the `IDistCollectiveLayer` primitives required by the varied parallelization methods. The rest of this put up focuses on context parallelism, which straight addresses the dominant price in fashionable generative media pipelines: long-sequence consideration.<\/p>\n<h4 class=\"wp-block-heading\">Context parallelism for generative media<\/h4>\n<p class=\"wp-block-paragraph\">Diffusion-based picture and video era pipelines spend a big fraction of their compute and reminiscence price range inside consideration blocks working over lengthy token sequences. A high-resolution picture latent or a multi-frame video clip can produce sequences of tens of hundreds of tokens per block, and a focus scales quadratically with sequence size.<\/p>\n<h4 class=\"wp-block-heading\">AllGather KV<\/h4>\n<p class=\"wp-block-paragraph\">Context parallelism partitions the sequence throughout GPUs. Every rank processes a slice of the queries (Q) comparable to its sequence partition. A simple method to implement context parallelism is the AllGather KV method, the place ranks alternate their key (Ok) and worth (V) shards via an AllGather collective earlier than computing native consideration, enabling every rank to attend over the total sequence. The result&#8217;s a per-rank consideration output protecting the total sequence at the price of one further collective per consideration block, whereas the native Q \u00d7 K\u1d40 matrix multiplication shrinks proportionally to the variety of ranks.<\/p>\n<p class=\"wp-block-paragraph\">For video and high-resolution picture diffusion, this trade-off compounds favorably throughout denoising steps. Communication overhead per step stays bounded by the sequence-dimension AllGather, whereas compute and reminiscence financial savings apply to each consideration layer in each step.<\/p>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391af8bb&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391af8bb\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"939\" height=\"343\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism.webp\" alt=\"An image showing that context parallelism partitions a token sequence across GPUs along the sequence dimension. Each rank processes a slice of Q locally. Before attention, ranks run AllGather on K and V so every slice can attend over the full sequence.\" class=\"wp-image-118985\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism.webp 939w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-179x65.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-300x110.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-768x281.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-625x228.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-645x236.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-500x183.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-160x58.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-362x132.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-301x110.png 301w\" sizes=\"(max-width: 939px) 100vw, 939px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"939\" height=\"343\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism.webp\" alt=\"An image showing that context parallelism partitions a token sequence across GPUs along the sequence dimension. Each rank processes a slice of Q locally. Before attention, ranks run AllGather on K and V so every slice can attend over the full sequence.\" class=\"lazyload wp-image-118985\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism.webp 939w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-179x65.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-300x110.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-768x281.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-625x228.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-645x236.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-500x183.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-160x58.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-362x132.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/KV-Context-Parallelism-301x110.png 301w\" data-sizes=\"(max-width: 939px) 100vw, 939px\"\/><figcaption class=\"wp-element-caption\">Determine 2. AllGather KV technique for context parallelism<\/figcaption><\/figure>\n<\/div>\n<h4 class=\"wp-block-heading\">Ring Consideration<\/h4>\n<p class=\"wp-block-paragraph\">Context parallelism might be applied in numerous methods, every presenting distinct trade-offs.\u00a0<\/p>\n<p class=\"wp-block-paragraph\">One potential enchancment over the AllGather KV methodology is Ring Consideration, the place communication and computation are overlapped. This allows every GPU to course of its native Q concurrently because the Ok and V repeatedly stream previous in a hoop topology. Ring Consideration additionally reduces the reminiscence footprint: utilizing a web-based softmax, the full-size Ok and V tensors don&#8217;t have to be materialized on any GPU. Learn the Ring Consideration with Blockwise Transformers for Close to-Infinite Context article to be taught extra about Ring Consideration.\u00a0<\/p>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b05a0&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b05a0\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1999\" height=\"670\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1.webp\" alt=\"An image showing an alternative implementation of context parallelism, using Ring Attention. The image shows that only partial-sized K and V are present on any given GPU, resulting in peak memory reduction.\" class=\"wp-image-119049\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1.webp 1999w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-179x60.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-300x101.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-768x257.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-625x209.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-1536x515.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-645x216.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-500x168.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-160x54.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-362x121.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-328x110.png 328w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-1024x343.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-960x322.png 960w\" sizes=\"(max-width: 1999px) 100vw, 1999px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1999\" height=\"670\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1.webp\" alt=\"An image showing an alternative implementation of context parallelism, using Ring Attention. The image shows that only partial-sized K and V are present on any given GPU, resulting in peak memory reduction.\" class=\"lazyload wp-image-119049\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1.webp 1999w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-179x60.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-300x101.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-768x257.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-625x209.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-1536x515.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-645x216.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-500x168.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-160x54.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-362x121.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-328x110.png 328w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-1024x343.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Ring-Attention-1-960x322.png 960w\" data-sizes=\"(max-width: 1999px) 100vw, 1999px\"\/><figcaption class=\"wp-element-caption\">Determine 3. Ring Consideration technique for context parallelism<\/figcaption><\/figure>\n<\/div>\n<h4 class=\"wp-block-heading\">DeepSpeed Ulysses<\/h4>\n<p class=\"wp-block-paragraph\">For lengthy context (tens of hundreds of tokens), an alternate context parallelism implementation method is DeepSpeed Ulysses. It initially partitions particular person samples alongside the sequence dimension throughout collaborating GPUs. Earlier than the eye computation, it employs an all-to-all communication collective on the partitioned Q, Ok, and V.<\/p>\n<p class=\"wp-block-paragraph\">This ensures that every GPU receives the total sequence size, however just for a non-overlapping subset of the eye heads, enabling them to compute consideration in parallel. Lastly, a second all-to-all communication gathers the outcomes throughout the eye heads whereas repartitioning them alongside the sequence dimension. Learn extra about context parallelism for lengthy context within the article DeepSpeed Ulysses: System Optimizations for Enabling Coaching of Excessive Lengthy Sequence Transformer Fashions.<\/p>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b12d4&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b12d4\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"2048\" height=\"594\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses.webp\" alt=\"An image showing an alternative implementation of context parallelism, using DeepSpeed Ulysses. The image illustrates the dual all-to-all communication steps that swap the parallelism dimension from the sequence length to the attention heads right before the attention block, and then back to the sequence length immediately afterward.\" class=\"wp-image-119015\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses.webp 2048w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-179x52.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-300x87.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-768x223.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-625x181.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-1536x446.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-645x187.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-500x145.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-160x46.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-362x105.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-379x110.png 379w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-1024x297.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-960x278.png 960w\" sizes=\"(max-width: 2048px) 100vw, 2048px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"2048\" height=\"594\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses.webp\" alt=\"An image showing an alternative implementation of context parallelism, using DeepSpeed Ulysses. The image illustrates the dual all-to-all communication steps that swap the parallelism dimension from the sequence length to the attention heads right before the attention block, and then back to the sequence length immediately afterward.\" class=\"lazyload wp-image-119015\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses.webp 2048w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-179x52.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-300x87.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-768x223.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-625x181.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-1536x446.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-645x187.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-500x145.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-160x46.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-362x105.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-379x110.png 379w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-1024x297.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/DeepSpeed-Ulysses-960x278.png 960w\" data-sizes=\"(max-width: 2048px) 100vw, 2048px\"\/><figcaption class=\"wp-element-caption\">Determine 4. DeepSpeed Ulysses technique for context parallelism<\/figcaption><\/figure>\n<\/div>\n<h2 id=\"benchmarks_media_generation_with_context_parallelism_in_c++\u00a0\" class=\"wp-block-heading\">Benchmarks: Media era with context parallelism in C++\u00a0<\/h2>\n<p class=\"wp-block-paragraph\">The next benchmarks consider multi-device TensorRT inference for media era workloads meant for C++ manufacturing deployment. Two consultant generative AI pipelines are used: a video era pipeline primarily based on NVIDIA Cosmos 3 and a picture era pipeline primarily based on FLUX.1.<\/p>\n<p class=\"wp-block-paragraph\">These pipelines had been first authored in PyTorch, then transformed out of the framework utilizing Torch-TensorRT to supply NVIDIA TensorRT engines appropriate for deployment in C++ inference functions. This workflow permits builders to retain PyTorch because the mannequin growth atmosphere whereas deploying optimized TensorRT engines in manufacturing techniques.<\/p>\n<p class=\"wp-block-paragraph\">The benchmarks evaluate end-to-end latency throughout totally different context parallelism methods: AllGather KV, Ring Consideration, and Ulysses. All outcomes had been collected on a single node with 8 GPUs.<\/p>\n<h3 id=\"video_generation_with_nvidia_cosmos_3\u00a0\" class=\"wp-block-heading\">Video era with NVIDIA Cosmos 3\u00a0<\/h3>\n<p class=\"wp-block-paragraph\">The NVIDIA Cosmos mannequin platform is a world basis mannequin platform, and the Cosmos3-Nano mannequin can generate photographs, video, audio, and different codecs primarily based on multimodal inputs, together with textual content, photographs, and video. We used the instance immediate file for our benchmarks. Based mostly on these benchmarks, Ulysses is the clear winner when a diffusion mannequin has excessively lengthy context lengths (within the order of tens of hundreds of enter tokens).<\/p>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b21a7&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b21a7\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1196\" height=\"724\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E.webp\" alt=\"A column chart showing the latency of different context parallelism strategies on 1,2,4 and 8 GPUs. The image shows that the latency scales well using both the Ulysses and the AllGather KV strategy.\" class=\"wp-image-118993\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E.webp 1196w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-179x108.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-300x182.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-768x465.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-625x378.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-645x390.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-496x300.png 496w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-149x90.png 149w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-362x219.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-182x110.png 182w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-1024x620.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-892x540.png 892w\" sizes=\"(max-width: 1196px) 100vw, 1196px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1196\" height=\"724\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E.webp\" alt=\"A column chart showing the latency of different context parallelism strategies on 1,2,4 and 8 GPUs. The image shows that the latency scales well using both the Ulysses and the AllGather KV strategy.\" class=\"lazyload wp-image-118993\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E.webp 1196w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-179x108.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-300x182.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-768x465.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-625x378.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-645x390.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-496x300.png 496w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-149x90.png 149w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-362x219.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-182x110.png 182w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-1024x620.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-E2E-892x540.png 892w\" data-sizes=\"(max-width: 1196px) 100vw, 1196px\"\/><figcaption class=\"wp-element-caption\">Determine 5. NVIDIA Cosmos 3 E2E latencies in milliseconds on N GPUs with totally different CP methods<\/figcaption><\/figure>\n<\/div>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b2c76&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b2c76\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1222\" height=\"766\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone.webp\" alt=\"A column chart showing the scaling of different context parallelism strategies on 1,2,4 and 8 GPUs.\" class=\"wp-image-118994\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone.webp 1222w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-179x112.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-300x188.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-768x481.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-625x392.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-645x404.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-479x300.png 479w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-144x90.png 144w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-362x227.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-175x110.png 175w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-1024x642.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-861x540.png 861w\" sizes=\"(max-width: 1222px) 100vw, 1222px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1222\" height=\"766\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone.webp\" alt=\"A column chart showing the scaling of different context parallelism strategies on 1,2,4 and 8 GPUs.\" class=\"lazyload wp-image-118994\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone.webp 1222w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-179x112.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-300x188.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-768x481.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-625x392.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-645x404.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-479x300.png 479w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-144x90.png 144w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-362x227.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-175x110.png 175w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-1024x642.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Cosmos-3-backbone-861x540.png 861w\" data-sizes=\"(max-width: 1222px) 100vw, 1222px\"\/><figcaption class=\"wp-element-caption\">Determine 6. NVIDIA Cosmos 3 spine speedup on GPUs with totally different context parallelism methods<\/figcaption><\/figure>\n<\/div>\n<div class=\"wp-block-image is-style-default\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b37c8&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b37c8\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1000\" height=\"300\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison.gif\" alt=\"Side-by-side images of a robotic arm cleaning a dirty plate with a sponge, with some dishes visible in the background. The two images look similar. &#10;\" class=\"wp-image-119027\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison.gif 1000w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-179x54.gif 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-300x90.gif 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-768x230.gif 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-625x188.gif 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-645x194.gif 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-500x150.gif 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-160x48.gif 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-362x109.gif 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-367x110.gif 367w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-960x288.gif 960w\" sizes=\"(max-width: 1000px) 100vw, 1000px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1000\" height=\"300\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison.gif\" alt=\"Side-by-side images of a robotic arm cleaning a dirty plate with a sponge, with some dishes visible in the background. The two images look similar. &#10;\" class=\"lazyload wp-image-119027\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison.gif 1000w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-179x54.gif 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-300x90.gif 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-768x230.gif 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-625x188.gif 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-645x194.gif 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-500x150.gif 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-160x48.gif 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-362x109.gif 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-367x110.gif 367w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Comparison-960x288.gif 960w\" data-sizes=\"(max-width: 1000px) 100vw, 1000px\"\/><figcaption class=\"wp-element-caption\">Determine 7. Pattern outputs of the NVIDIA Cosmos 3 mannequin on 8 GPUs with totally different CP methods<\/figcaption><\/figure>\n<\/div>\n<h3 id=\"image_generation_with_flux1\" class=\"wp-block-heading\">Picture era with Flux.1<\/h3>\n<p class=\"wp-block-paragraph\">The FLUX.1-dev mannequin from Black Forest Labs can generate photographs from textual content descriptions. We used the immediate: \u201ca wonderful {photograph} of Mt. Fuji throughout cherry blossom\u201d for our benchmarks. Based mostly on the benchmarks, the Ulysses technique is the winner within the case of picture era as properly, however it\u2019s value noting that Ring Consideration additionally scaled properly to 4 GPUs.<\/p>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b43ba&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b43ba\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1500\" height=\"748\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1.webp\" alt=\"A column chart showing the latency of different context parallelism strategies on 1,2,4 and 8 GPUs. The image shows that the lowest latency is achieved by applying the Ulysses strategy.\" class=\"wp-image-119020\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1.webp 1500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-179x89.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-300x150.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-768x383.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-625x312.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-645x322.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-500x249.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-160x80.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-362x181.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-221x110.png 221w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-1024x511.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-960x479.png 960w\" sizes=\"(max-width: 1500px) 100vw, 1500px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1500\" height=\"748\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1.webp\" alt=\"A column chart showing the latency of different context parallelism strategies on 1,2,4 and 8 GPUs. The image shows that the lowest latency is achieved by applying the Ulysses strategy.\" class=\"lazyload wp-image-119020\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1.webp 1500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-179x89.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-300x150.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-768x383.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-625x312.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-645x322.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-500x249.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-160x80.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-362x181.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-221x110.png 221w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-1024x511.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Backbone-1-960x479.png 960w\" data-sizes=\"(max-width: 1500px) 100vw, 1500px\"\/><figcaption class=\"wp-element-caption\">Determine 8. Flux E2E latencies in milliseconds on N GPUs with totally different CP methods<\/figcaption><\/figure>\n<\/div>\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b4f19&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b4f19\" class=\"wp-block-image size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1496\" height=\"658\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup.webp\" alt=\"A column chart showing the scaling of different context parallelism strategies on 1,2,4 ,and 8 GPUs.\" class=\"wp-image-119021\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup.webp 1496w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-179x79.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-300x132.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-768x338.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-625x275.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-645x284.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-500x220.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-160x70.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-362x159.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-250x110.png 250w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-1024x450.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-960x422.png 960w\" sizes=\"(max-width: 1496px) 100vw, 1496px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1496\" height=\"658\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup.webp\" alt=\"A column chart showing the scaling of different context parallelism strategies on 1,2,4 ,and 8 GPUs.\" class=\"lazyload wp-image-119021\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup.webp 1496w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-179x79.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-300x132.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-768x338.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-625x275.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-645x284.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-500x220.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-160x70.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-362x159.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-250x110.png 250w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-1024x450.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-Speedup-960x422.png 960w\" data-sizes=\"(max-width: 1496px) 100vw, 1496px\"\/><figcaption class=\"wp-element-caption\">Determine 9. Flux spine speedup on GPUs with totally different CP methods<\/figcaption><\/figure>\n<div class=\"wp-block-image\">\n<figure data-wp-context=\"{&quot;imageId&quot;:&quot;6a4ad391b5bc9&quot;}\" data-wp-interactive=\"core\/image\" data-wp-key=\"6a4ad391b5bc9\" class=\"aligncenter size-full wp-lightbox-container\"><img decoding=\"async\" width=\"1540\" height=\"596\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies.webp\" alt=\"A side-by-side comparison of the outputs of AllGather KV, Ring Attention ,and Ulysses CP strategies. The output images look very similar to each other. All 3 output images show Mt. Fuji with a cherry tree branch in the foreground.\" class=\"wp-image-119016\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies.webp 1540w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-179x69.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-300x116.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-768x297.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-625x242.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-1536x594.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-645x250.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-500x194.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-160x62.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-362x140.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-284x110.png 284w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-1024x396.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-960x372.png 960w\" sizes=\"(max-width: 1540px) 100vw, 1540px\"\/><img loading=\"lazy\" decoding=\"async\" width=\"1540\" height=\"596\" data-wp-class--hide=\"state.isContentHidden\" data-wp-class--show=\"state.isContentVisible\" data-wp-init=\"callbacks.setButtonStyles\" data-wp-on--click=\"actions.showLightbox\" data-wp-on--load=\"callbacks.setButtonStyles\" data-wp-on--pointerdown=\"actions.preloadImage\" data-wp-on--pointerenter=\"actions.preloadImageWithDelay\" data-wp-on--pointerleave=\"actions.cancelPreload\" data-wp-on-window--resize=\"callbacks.setButtonStyles\" src=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies.webp\" alt=\"A side-by-side comparison of the outputs of AllGather KV, Ring Attention ,and Ulysses CP strategies. The output images look very similar to each other. All 3 output images show Mt. Fuji with a cherry tree branch in the foreground.\" class=\"lazyload wp-image-119016\" srcset=\"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies.webp 1540w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-179x69.png 179w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-300x116.png 300w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-768x297.png 768w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-625x242.png 625w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-1536x594.png 1536w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-645x250.png 645w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-500x194.png 500w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-160x62.png 160w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-362x140.png 362w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-284x110.png 284w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-1024x396.png 1024w, https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/Flux-E2E-latencies-960x372.png 960w\" data-sizes=\"(max-width: 1540px) 100vw, 1540px\"\/><figcaption class=\"wp-element-caption\">Determine 10. Pattern outputs of the Black Forest Lab Flux.1 mannequin on 8 GPUs with totally different CP methods<\/figcaption><\/figure>\n<\/div>\n<h2 id=\"getting_started_using_tensorrt_with_the_multi-device_feature\" class=\"wp-block-heading\">Getting began utilizing TensorRT with the multi-device function<\/h2>\n<p class=\"wp-block-paragraph\">TensorRT helps multi-device inference, enabling a single community to execute throughout a number of GPUs via built-in distributed communication primitives. The core workflow is much like that of single-device TensorRT. The distinction is that the community can now embody distributed communication layers.\u00a0<\/p>\n<p class=\"wp-block-paragraph\">On this information, it\u2019s assumed that the identical community is deployed on all GPU ranks, however this isn\u2019t a strict requirement, and, in concept, every rank can run a distinct mannequin.<\/p>\n<p class=\"wp-block-paragraph\">A working pattern is supplied within the TensorRT repository. The next information gives a step-by-step description of  use the brand new multi-device function.<\/p>\n<p class=\"wp-block-paragraph\">Conditions<\/p>\n<p>Create a community for multi-device inference<\/p>\n<p class=\"wp-block-paragraph\">On the community stage, multi-device inference is enabled via IDistCollectiveLayer for cross-GPU communication. Collective operations might be added on to a TensorRT community utilizing INetworkDefinition::addDistCollective:<\/p>\n<div class=\"wp-block-syntaxhighlighter-code \">\nutilizing namespace nvinfer1;<br \/>\n\/\/ create empty community<br \/>\nauto community =<br \/>\n  std::unique_ptr(builder-&gt;createNetworkV2(<br \/>\n  1U &lt;&lt; static_cast(kSTRONGLY_TYPED)));<br \/>\nauto* enter =<br \/>\n  network-&gt;addInput(&#8220;enter&#8221;, DataType::kFLOAT, Dims2{3, 4});<br \/>\nITensor&amp; inputTensor = *network-&gt;getInput(0);<br \/>\nauto* collectiveLayer = network-&gt;addDistCollective(<br \/>\n    inputTensor,<br \/>\n    CollectiveOperation::kALL_REDUCE,<br \/>\n    ReduceOperation::kSUM,<br \/>\n    -1,       \/\/ root: -1 for collectives and not using a root rank<br \/>\n    nullptr,  \/\/ teams: nullptr means all ranks take part<br \/>\n    0         \/\/ groupSize<br \/>\n);<\/p>\n<p>\/\/ set the world dimension aka complete variety of GPUs<br \/>\ncollectiveLayer-&gt;setNbRanks(8);<\/p>\n<\/div>\n<p class=\"wp-block-paragraph\">For discount collectives reminiscent of ALL_REDUCE, REDUCE, and REDUCE_SCATTER, specify a legitimate ReduceOperation, reminiscent of kSUM. For non-reduction collectives reminiscent of ALL_GATHER, BROADCAST, ALL_TO_ALL, GATHER, and SCATTER, use ReduceOperation::kNONE. Root-based operations, together with BROADCAST, REDUCE, GATHER, and SCATTER, require a legitimate root rank.<\/p>\n<p>Construct an engine<\/p>\n<div class=\"wp-block-syntaxhighlighter-code \">\n\/\/ create builder config<br \/>\nauto builderConfig = std::unique_ptr(builder-&gt;createBuilderConfig());<br \/>\n\/\/ construct engine<br \/>\nauto serializedEngine =  std::unique_ptr(builder-&gt;buildSerializedNetwork<br \/>\n(*community, *builderConfig));\n<\/div>\n<p>Create execution context<\/p>\n<div class=\"wp-block-syntaxhighlighter-code \">\nauto runtime = std::unique_ptr(createInferRuntime(<br \/>\npattern::gLogger.getTRTLogger()));\n<\/div>\n<p>Bind IO tensors<\/p>\n<div class=\"wp-block-syntaxhighlighter-code \">\n char const* inputName = engine-&gt;getIOTensorName(0);<br \/>\n   char const* outputName = engine-&gt;getIOTensorName(1);<\/p>\n<p>   std::vector const&amp; inputChunk = (rank == 0) ? config.rank0Input : config.rank1Input;<br \/>\n   std::vector outputChunk(config.outputElementCount, 0.0F);<\/p>\n<p>   size_t const inputBytes = inputChunk.dimension() * sizeof(float);<br \/>\n   size_t const outputBytes = outputChunk.dimension() * sizeof(float);<\/p>\n<p>   void* dInput = nullptr;<br \/>\n   void* dOutput = nullptr;<br \/>\n   CHECK_CUDA(cudaMalloc(&amp;dInput, inputBytes));<br \/>\n   CHECK_CUDA(cudaMalloc(&amp;dOutput, outputBytes));<\/p>\n<p>   \/\/ Copy enter information to GPU asynchronously<br \/>\n   CHECK_CUDA(cudaMemcpyAsync(dInput, inputChunk.information(), inputBytes, cudaMemcpyHostToDevice, stream));<\/p>\n<p>   \/\/ Set enter\/output tensor addresses within the execution context<br \/>\n   context-&gt;setInputTensorAddress(inputName, dInput);<br \/>\n   context-&gt;setTensorAddress(outputName, dOutput);<br \/>\n   context-&gt;setInputShape(inputName, Dims2{kINPUT_ROWS, kINPUT_COLS});\n<\/p><\/div>\n<p>Set communicator and enqueue inference<\/p>\n<div class=\"wp-block-syntaxhighlighter-code \">\ncontext-&gt;setCommunicator(comm);<br \/>\ncontext-&gt;enqueueV3(stream);\n<\/div>\n<p class=\"wp-block-paragraph\">Be aware: the NCCL communicator should additionally stay legitimate for the lifetime of the execution context that makes use of it.<\/p>\n<p>Kick off inference<\/p>\n<p class=\"wp-block-paragraph\">Run the appliance with OpenMPI on 8 GPUs. Every rank selects its native CUDA system, initializes NCCL, creates its personal TensorRT engine, creates its personal execution context, and attaches the NCCL communicator.<\/p>\n<div class=\"wp-block-syntaxhighlighter-code \">\nmpirun -np 8 bash -lc &#8216;export TRT_MY_RANK=$OMPI_COMM_WORLD_RANK;<br \/>\nexport TRT_WORLD_SIZE=$OMPI_COMM_WORLD_SIZE;<br \/>\nexport TRT_NCCL_ID_FILE=\/tmp\/nccl_id.txt;<br \/>\n.\/sample_dist_collective &#8211;op all_reduce&#8217;\n<\/div>\n<h2 id=\"learn_more\" class=\"wp-block-heading\">Be taught extra<\/h2>\n<p class=\"wp-block-paragraph\">If you wish to be taught extra concerning the matters launched on this article, we included some helpful hyperlinks for additional studying.<\/p>\n<p class=\"wp-block-paragraph\">NCCL: NVIDIA Collective Communications Library (NCCL)<\/p>\n<p class=\"wp-block-paragraph\">Parallelism:<\/p>\n<p class=\"wp-block-paragraph\">NVIDIA TensorRT:<\/p>\n<p class=\"wp-block-paragraph\">NVIDIA Torch-TensorRT: Torch-TensorRT Documentation<\/p>\n<\/div>\n<p><br \/>\n<br \/><a href=\"https:\/\/developer.nvidia.com\/blog\/scaling-ai-inference-across-multiple-gpus-using-nvidia-tensorrt-with-multi-device-inference-support\/\">Source link <\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>Generative AI workloads are quickly outgrowing the reminiscence and compute price range of single GPUs. For inference builders constructing media era pipelines, the problem is scaling throughout a number of units with out sacrificing the crucial optimizations\u2014like kernel fusions, reminiscence planning, and quantization\u2014that NVIDIA TensorRT delivers for manufacturing deployments.\u00a0 Multi-device inference help, a brand new [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":1924,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"fifu_image_url":"https:\/\/developer-blogs.nvidia.com\/wp-content\/uploads\/2026\/06\/AI-Inference.webp","fifu_image_alt":"","jnews-multi-image_gallery":[],"jnews_single_post":[],"jnews_primary_category":[],"jnews_override_bookmark_settings":[],"jnews_social_meta":[],"jnews_override_counter":[],"footnotes":""},"categories":[3],"tags":[1597,1068,2424,2422,81,325,163,2423],"class_list":["post-1922","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ai-platforms-apps","tag-gpus","tag-inference","tag-multidevice","tag-multiple","tag-nvidia","tag-scaling","tag-support","tag-tensorrt"],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.7 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Scaling AI Inference Throughout A number of GPUs Utilizing NVIDIA TensorRT with Multi-System Inference Help - Future News 24<\/title>\n<meta name=\"description\" content=\"Generative AI workloads are rapidly outgrowing the memory and compute budget of single GPUs. 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